The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in the background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.
A protocol, referred to as either the hopping bus protocol or the MoChi protocol, has been developed for optimizing the efficiency of intra-chip and inter-chip communications of System-on-Chips (“SoCs”). Background of how the hopping bus protocol enables intra-chip and inter-chip communications between discrete SoCs and their components is described in commonly owned U.S. patent application Ser. No. 14/564,499 (published as U.S. Patent Application Publication No. 2015/0169495) (Referred to herein as the “Hopping Bus Reference”), the contents of which are hereby incorporated by reference herein in their entirety. Further improvements to the MoChi protocol are the subject of this disclosure.
In related protocols, the address scheme of most of the components of a system—that is, the various SoCs or chips of the system, was not configurable, and instead, was fixed at the time of manufacture of each chip. Moreover, to the extent that the address scheme was configurable, this was only for Peripheral Component Interconnect Express (“PCIe”) components, and these components were only configurable after boot-up of an operating system.
Conventional integrated circuit communications protocols, such as AXI (AMBA eXtensible Interface, where AMBA stands for Advanced Microcontroller Bus Architecture), facilitate point-to-point communications between components. These protocols suffer inefficiencies because, if two components are to intercommunicate, wires that interconnect the two components must be implemented, which takes up chip space and is expensive.